A direct digital synthesis (DDS) synthesizer circuit often incorporates a digital-to-time converter (DTC) to produce a square wave at its output. The output of the DDS based on a DTC can be used in a radio transceiver to provide a local oscillator (LO) signal. Although common problems often associated with using a DDS involve a tolerable spurious emissions level (spurs) and noise floor, the use of DDS in a radio transceiver also offers many benefits since the DDS output frequency can be tuned over a very wide range with zero lock time.
With regard to spurious emissions by the DDS, there are two sources of error that cause spurs in the spectrum of the output square wave. These sources of error include both mismatch error and quantization error. Mismatch error refers to the DTC error that is due to process mismatch delay and locked loop error. Quantization error is the error or distortion introduced through the quantization process. Although there are existing methods that use dither to eliminate the contribution of the quantization error to the spurs it does nothing to mitigate the mismatch error. As is well known in the art, dithering is done by adding noise of a level less than the least-significant bit before rounding. The added noise has the effect of spreading the many short-term errors across the spectrum as broadband noise. Small improvements can be made to a dithering algorithm such as shaping the noise to areas where it is less objectionable, but the process remains simply one of adding the minimal amount of noise necessary to increase performance.
One example of this type of dithering approach is shown in U.S. Pat. No. 4,933,890 which is herein incorporated by reference. Prior art FIG. 1 illustrates a DDS 100 used for quantizing the output of a digital block 101. A low level noise, or dither, is injected using a dither source 103 to an adder 105 in order to eliminate the quantization error from being periodic. The quantizer 107 rounds the sum of the digital block 101 and dither source 103 to the nearest multiple of 2−m, where m is the bit width of the input of the DTC 111.
Prior art FIG. 2 shows timing diagrams for the DDS 100. Line A shows the reference clock. Line B shows the v(n) output of the digital block 101, a succession of fractional numbers with k bits after the point. Line C shows the en1(n) output of the digital block, an enable signal for indicating clock cycles that are enabled to produce a pulse. The outputs of the digital block, v(n) and en1(n), describe a pulse waveform that can be considered an ideal (no quantization or mismatch error) version of the output of the synthesizer. The signal v(n) is proportional to the pulse delays for the pulses contained in the ideal pulse waveform. Line D shows the ideal pulse waveform. It consists of a train of pulses. The pulse width equals Tclk/2, the same as the pulse width of the reference clock. The rising edges of the pulses are delayed with respect to the rising edges of the reference clock, where the amounts of delay are proportional to the values of v(n). The changes, i.e. updates, in the signals v(n) and en1(n) occur at rising edges of the reference clock. In the interval between 2 rising clock edges, the ideal pulse waveform contains a rising edge only if en1(n)=1. It can be said that en1(n)=1 enables the cycle to produce a pulse, and to position the rising edge of the pulse in time before the end of the cycle. Specifically the pulse is positioned so the time delay from the rising edge of the clock to the rising edge of the pulse equals v(n)×Tclk. v(n) is a fractional number between 0 and 1-2−k.
The bit width of the output of the digital block, k, sets the resolution for delaying the pulses in the idealized pulse waveform, i.e. setting the period of the idealized pulse waveform. In the example waveform of FIG. 2, line D, the period is (1+3/32)×Tclk. The period, Tout, is limited by the resolution for setting the period and by Tclk≦Tout≦max{Tout}. The maximal Tout, i.e. max{Tout}, is due to some hardware or software consideration as will depend on the implementation. Since the output frequency of the idealized pulse waveform, Fout, is the inverse of Tout, k also sets the resolution for setting Fout in the range min{Fout}≦Fout≦Fclk, where min{Fout}=(max{Tout})−1.
The bit width of the output of the digital block, k, exceeds the bit width of the input of the DTC, m. In FIG. 2, k=5 because the output of the digital block v(n) is a succession of 5-bit binary numbers (fractional numbers with denominator 25 or 32) and m=3 because the input of the DTC w(n) is a succession of 3-bit binary numbers (fractional numbers with denominator 23 or 8.) Although FIG. 2 is for illustration purposes, a typical application in practice is likely to have bit widths greater than k=5 and m=3. Since the bit width of the output of the digital block exceeds the bit width of the input of the DTC quantization is a requirement, and is carried out by the dither source 103, summer 105, and quantizer 107 as described herein. Because of the quantization, exact timing is not maintained in terms of the pulse delay times. This timing error causes jitter, and the quantization error energy appears in the spectrum of the output of the DTC. Note, however, that the output of the DTC has the same frequency resolution as the idealized pulse waveform, and as mentioned above, this resolution is set by the bit width of the digital block output v(n).
As noted herein, the quantizer 107 rounds the sum of the digital block 101 and dither source 103. Lines E and F show the 2's complement outputs of the dither source and summer. The dither source is a discrete random variable uniformly distributed in the range −2−m−1≦d(n)<2−m−1.
It will be recognized by those skilled in the art that the limits of the range are plus/minus one-half quantization interval, or 2−4=1/16 in FIG. 2. Line F shows the 2's complement output of the summer 105. As an example, in the second cycle in FIG. 2 v(n)=3/32. Then v(n)+d(n) is in the range 1/32≦v(n)+d(n)<5/32, and since the quantizer rounds to the nearest multiple of 2−m, or 1/8, it follows that q(n)=0 or 1/8.
Thus, it can be shown that the probability that the quantizer rounds to q(n)=0 is 1/4 and to q(n)=1/8 is 3/4. In the ensemble average of cycles with v(n)=3/32, the average error is calculated as −3/32×(1/4)+1/32×(3/4)=0.
Those skilled in the art will further recognize that in the ensemble average of a large number of cycles the timing error due to quantization approaches zero. Due to rounding, the quantizer output range is 0 to 1.000 and requires a digit in front of the point. For the DTC input, on the other hand, there is no digit in front of the point and the range is 0 to the binary number 0.111, representing 7/8. w(n)=1.000 is not a valid DTC input. w(n)=1.000 is not typically a valid DTC input for implementations of DTC since if it were valid, it would correspond to a pulse delayed by Tclk, i.e., one clock period, with respect to the rising edge of clock cycle n. An equivalent pulse can also be produced with w(n+1)=0, i.e. a delay of zero with respect to the rising edge of clock cycle n+1. The signals q(n) and en1(n) couple to the input of the DTC through the modulo block 109. Lines H and I in FIG. 2 show the outputs of the modulo block. In a cycle in which q(n) does not equal 1.000 or don't_care, the modulo block behaves as a transparent pass-through. In other words in such a cycle w(n)=q(n) and en2(n)=en1(n). In a cycle in which q(n)=1.000 the modulo block outputs w(n)=don't_care and en2(n)=0. Furthermore, in the next clock cycle, cycle # n+1, the modulo block outputs w(n+1)=0 and en2(n+1)=1. In a cyle in which q(n)=don't_care, the modulo block passes-through w(n)=don't_care and en2(n)=en1(n)=0 UNLESS q(n−1)=1.000 in the prior clock cycle.
Finally, a high resolution digital-to-time converter (DTC) 111 is used to finely locate each edge of the output signal 113 at the correct instant in the time domain. As is well known in the art, the time resolution of the DTC 111 directly determines the spectral purity of output signal 113. The output signal 113 is a square wave whose spectrum contains spurs and measurable noise floor. The DTC produces a pulse at the output, delayed with respect to the reference clock. Line J of FIG. 2 shows that the width for the pulses is Tclk/2. The ideal amount of time delay may be measured from the rising edge of the reference clock to the rising edge of the output pulse and equals w(n)×Tclk.
The mathematical sum of the ideal waveform in line D in FIG. 2 and quantization error shown in Line K, as well as the other error terms such as DTC mismatch error, equals the actual synthesizer output, Out(t). As shown in line K, the quantization error has no pattern. Any pattern in the quantization error would cause spectral lines, or spurs, in the spectrum of Out(t). The dither eliminates the quantization error from having a pattern and therefore eliminates the quantization error from contributing to spurs in the spectrum of Out(t). DTC error is the error in the delay time of the output pulses due to DTC non-idealities. Two types of DTC error are DTC mismatch error and DTC thermal noise or device noise error. DTC mismatch error refers to error that has a discrete distribution, i.e. finite set of possible values, and is correlated with w(n), the signal at the input of the DTC. The DTC mismatch error can for example be due to finite matching accuracy for taps in a DTC implemented using a tapped delay line. For each element in the set of possible w(n) there is an associated element in the set of possible mismatch error values. The mismatch error for a pulse generated in response to w(n) in one cycle equals the element associated with the value of w(n) in the cycle with a probability of 1.0. The DTC thermal noise on the other hand is random, not correlated with w(n). While the dither in the prior art system eliminates the contribution of the quantization error to the spurs, it does nothing to reduce the contribution of the mismatch error to the spurs.
One problem associated with the system as seen in FIG. 1 is that it uses dither where the maximum spur level depends on the DTC error. In a radio receiver, achieving spurious emissions low enough to use the DDS to produce the LO signal requires an extremely accurate DTC. Using current technology, such an accurate DTC is not practical making the prior art system very difficult to use in practical applications.
Therefore, the need exists to provide a DDS with improved quantization error and mismatch to reduce overall spurious emissions.